In U.S. Pat. No. 4,024,514, filed June 30, 1975, there is disclosed an SPS CCD memory wherein the serial input and output sections each has approximately twice the number of storage nodes as the number of channels contained in the main parallel storage section with data bits being transferred into and out of each of the channels of the main parallel storage section in one step.
U.S. Pat. No. 3,913,077, filed Apr. 17, 1974, describes an SPS CCD memory arranged in an interlaced or interleaved mode wherein data bits are alternately stored at even and odd storage nodes of the serial input and output sections with the data bits being transferred into and out of the main parallel storage section in two steps so that each storage node of the serial input and output sections serves one channel of the main parallel storage section.
U.S. Pat. No. 3,967,254, filed Nov. 18, 1974, illustrates an output gate electrode structure for transferring data bits from the main parallel storage section to the serial output section which may be used in an SPS CCD memory arranged in an interlaced or interleaved mode.
In commonly assigned U.S. Pat. No. 4,117,546, filed Dec. 30, 1977, there is disclosed an interlaced SPS CCD memory which uses a low number of different clock pulses to propagate the packets of charge through the channels.
It can be noted that in each of the SPS CCD memories or SPS charge transfer device (CTD) memories disclosed in the above identified patents at least one storage node and an associated transfer gate is provided in the serial input and output sections for each data bit channel contained in the main parallel storage section. Accordingly, the packing density of the channels in the main parallel storage section of the SPS CCD memory is not optimum since in known CCD technologies or processes the minimum combined length L of an electrode of a storage node and an electrode of an associated transfer gate is substantially longer than the minimum combined width W of a channel and a channel isolation medium or channel stop region required between adjacent parallel channels, i.e., L&gt;W. Stated in another way, the pitch of the input and output series registers limits the storage node or cell density in the main parallel storage section of the SPS CCD memories.